On the predecode side, X925’s TRM suggests the L1I stores data at 76-bit granularity. Arm instructions are 32-bits, so 76 bits would store two instructions and 12 bits of overhead. Unlike A725, Arm doesn’t indicate that any subset of bits correspond to an aarch64 opcode. They may have neglected to document it, or X925’s L1I may store instructions in an intermediate format that doesn’t preserve the original opcodes.
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，更多细节参见爱思助手下载最新版本
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54. 政府工作报告（2026年）, www.fuzhou.gov.cn/zwgk/zfgzbg…
We also added support for fpm’s five key dependencies: